Photosensitive or "pixel" cells and drive circuits for controlling those cells are known in the art. A typical drive circuit consists of a conventional buffer that is capable of propagating to a pixel cell or other circuit a voltage level that is no higher than a logic high voltage level. In CMOS circuits this voltage high level is often V.sub.DD. As discussed in more detail below, this limitation is disadvantageous in use with pixel cells and other types of circuits.
Referring to FIG. 1, a representative photosensitive cell 10 is shown. Cell 10 includes three transistors 12-14 (which are typically n-type field-effect transistors) and a light sensitive or "photo" diode 15. Transistors 12 and 13 are coupled to V.sub.DD and transistor 14 is coupled to the source of transistor 13. A row reset signal is applied to the gate of transistor 12 and a row select signal is applied to the gate of transistor 14.
In a typical mode of operation, the row reset line is asserted high to charge the parasitic capacitance of the reversed biased photo diode to a reset level. After diode output node 17 has stabilized, the row reset is pulled low, allowing photo induced charge carriers to discharge the photo diode at a rate proportional to the incident light intensity. After a specific exposure time, the row select line is asserted high allowing the voltage at node 17 to be sampled at the cell output node 19 (normally coupled to a column of pixel cell outputs), through source follower buffer transistor 13. The row reset signal is again asserted high and low to reset node 17 a second time. The reset level is sampled at output 19. The difference between the voltage level at output 19 after exposure to incident light and at a reset level is proportional to the incident light intensity.
The row reset signal is driven by a digital gate that limits the high level of row reset to V.sub.DD as this is typically the highest available supply voltage on a CMOS integrated circuit. While beneficial for some purposes, the use in a typical pixel cell of a row reset signal with a high level limited to V.sub.DD has disadvantageous aspects.
One disadvantageous aspect is that the dynamic range at output 19 is limited to a maximum of V.sub.DD -(2.times.the NMOS threshold, Vtn). One Vtn is lost at transistor 12 and the other is lost at transistor 13. Thus, dynamic range for a 3.3V V.sub.DD cell is approximately 3.3-(2.times.0.8) or 1.7 to 0.4 (the turn-off voltage of a current source transistor coupled to pixel column output 19). This results in a typical dynamic range magnitude of 1.3V.
Another disadvantageous aspect is that the row reset signal must be held high for a relatively long time, on the order of 100 microseconds, before node 17 reaches its final settled voltage due to sub-threshold leakage currents at transistor 12 as that transistor approaches its cutoff state. Due to timing constraints, imaging systems may be forced to use a shorter reset interval. Shorter reset intervals can in turn result in a difference between the "before exposure" reset and the "after exposure" reset signal strengths. The net effect is a memory of the previous captured image which can either add to or subtract from the present captured image, giving the appearance of a positive or negative ghost image superimposed on the desired image.